The Efficient Machine Vision Processing Of Multi-Core System

The rapid development and innovative breakthrough of robot technology, that makes the range more widely applications. Machine vision has always been a hot key issue in robotics research. Image processing in machine vision faces large amount of data, processing speed and other issues. With the advent of multi-core architecture, multi-core parallel technology has become a new means to improve the image processing speed.But the high-performance chip many-core systems to become one of the fast-growing power bottlenecks limit performance development. Due to the heat, the package, the external power supply capacity and other restrictions, many-core system chip’s power consumption will inevitably be affected. It is because power is limited, can not support all of the transistors while the chip is working properly, causing part of the processor must be switched off, the so-called "dark silicon" phenomenon. This phenomenon will lead directly to many-core system on a chip can achieve real performance much worse than ideal performance (such as speedup of parallel programs, etc.), and the gap in performance is still expanding.This paper focuses on image processing algorithms, one of the fast Fourier transform algorithm commonly used parallel and multi-core and many-core system architecture, the new chip power allocation algorithm in silicon in the dark background. The main results include:(1) FFT algorithm parallelizability analyzed, designed a two-dimensional fast Fourier transform algorithm for image processing. The experiments prove that the multi-core test environment, with a very significant acceleration effect. (2) In this paper, the power allocation for many-core systems is formulated to optimize the overall system performance over a power budget by tile level frequency scaling, which could be reduced to the bounded knapsack problem. Subsequently, the runtime power allocation methods, has been proposed, with a linear time complexity based on the parallel dynamic programming network. The experimental results have confirmed that, with low hardware overhead can reduce the application execution time by as much as 45% compared to other best known methods. Due to its superior scalability over other known methods, that is deemed as a suitable power allocation scheme for future large-scale many-core systems.