Low-cost Delta-sigma Frequency-locked Loop Design With High Frequency Accuracy

Production cost and power consumption reduction are two main objectives oftoday’s active research related to the communication filed. And frequency locked loopshave some advantages, such as wide locking range and easily digitizing, are extensiveapplied as auxiliary module, its limitation is the accuracy of FLL.This paper willintroduce a new FLL structure, which achieves highly digital design and high-precisionlow-cost, to meet the future applications demands.This design uses1-bit frequency detector (FD), which not only achieves a highprecision FLL in GHz band, but also avoids high precision TDC of ADPLL thatrequires advanced technology.This paper will firstly elaborate on an all-digital FLL(ADFLL), including moduledesign, loop structure, circuit implements, and its prototype is fabricated in0.18umCMOS, the simulation results and testing results will shows in the paper. It could beapplied in the wireless communication, such as FM-UWB.Furthermore, on the basis of this ADFLL, the paperproposed an improved version,which uses a PLL to realize the constant gain DCO. For the deficiencies of this ADFLL,the new FLL proposes several improvements to improve noise characteristics andfrequency accuracy, and it can be applied in the spread spectrum application, complywith the requirements of SATA and other wireline communication applications.