Study Of Memory Access Aware Mapping Algorithm For Networks-on-Chip

With the continuous development of semiconductor technology, more and more cores will be integrated onto a signal chip to offer high-computing-capacity and low-power-consumption processors. Conventional point-to-point and bus-based communication mechanism cannot afford the rapidly increasing on-chip communication. Networks-on-chip (NoC), which connects cores together by networks and offers packet switched communication among cores, provides very high on-chip communication bandwidth. It has been widely accepted that the NoC paradigm will be the default design choice for future large-scale multi-core processors.In contrast with the high on-chip communication bandwidth, the bandwidth between NoC chips and off-chip memory systems is still relatively low, which is usually the bottleneck of the overall system performance. A large number of tasks wait for accessing memory which leads to the decrease of system performance. SDRAM is commonly used for the off-chip memory because of its large memory capacity and high access speed. The accesses to different banks in SDRAM can be served simultaneously, thus exploring the access parallelization is a key to improve the communication efficiency of SDRAM.To address this communication bottleneck, we present a mapping algorithm named MA-MAP. The main idea of our algorithm is to organize the memory accesses in the way that the round-robin router will alternately send the accesses to different banks, by which the accesses can be served in parallel as much as possible. This algorithm optimizes for not only the on-chip communication, but also the off-chip communication efficiency. Our algorithm based on round-robin router with source-based routing which is very commonly used on NoC, it does not require any special hardware support.In this experiment, we chose NIRGAM NOC simulator to verify the effect of our mapping algorithm, we modify its functional and add some new modules in it, such as source node module and memory module.Experiments show that our algorithm can significantly improve the memory access efficiency, and eventually improve the overall system performance comparing with classical NoC mapping algorithms PBB and NMAP.