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Research Of Spiking Deep Neural Network Hardware Implementation Based On FPGA And System On Chip

Posted on:2017-10-15Degree:MasterType:Thesis
Country:ChinaCandidate:L YuFull Text:PDF
GTID:2348330509954183Subject:Master of Engineering
Abstract/Summary:PDF Full Text Request
Deep neural network is the state-of-the-art model in artificial neural network study now. Deep neural network exists problems of computation complexity and memory complexity. Therefore the von Neumann computers have the limitation of low efficiency and high power consumption in computing the deep neural network. Dedicated hardware for deep neural network computing will effectively address these disadvantages. This paper aims to design a deep neural network computing coprocessor for embedded system. This coprocessor can be used to achieve large scale deep neural network computing in real-time with low-power and high efficiency.By combining deep neural network with spiking neural network, this paper points out a Spiking Deep Neural Network model and its learning algorithm. Deep neural network model such as deep belief network model and convolutional neural network model have shown great performance in solving video and audio object recognition problems. Spiking neural network model is hardware-friendly and easy for hardware implementation. This paper describes a method for converting a deep neural network model into a Spiking Deep Neural Network model which can realize ultra-low power consumption in effective deep neural network model computing.This paper designs a Spiking Deep Neural Network memory and computing architecture. A sparse feed forward network is proposed to compute Spiking Deep Belief Network and Spiking Convolutional Neural Network in a universal architecture. Then an architecture based on index look-up table is designed to compute the sparse feed forward network. Multi-level pipeline and low-power design are used to improve the efficiency and reduce power consumption in hardware implementation.Based on the architecture above, this paper designs a configurable and low-power Spiking Deep Neural Network computing coprocessor. Then a comprehensive verification and analysis of the coprocessor is done. In the end of this paper, a prototype system which integrates Spiking Deep Neural Network computing coprocessor and ARM processor is designed and verified.
Keywords/Search Tags:Spiking Deep Neural Network, Index Look-up Table, SoC, Coprocessor
PDF Full Text Request
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