Research On Spin-Torque-Transfer Magnetic Tunnel Junction Modelin And Retention Register Using STT-MTJ

The fast development of portable devices and wearable devices has making people pay more and more attention to the flight time of devices. As for IC design, this means an increasing demand for low power. In addition, leakage power is more and more being a portion that cannot ignore in advanced processes. The most directive and effective method to do low power design is using Power Gating, shut down some modules that is not in use temporarily, making the standby power of shut down modules zero. But, with power shutting down, the state data in shut down modules is lost, which results in a longer recovery time.The solution to avoid data loses when shut down is using Retention Register. Conventional retention register using two power supplement and the data backup circuit uses Always-On power. When the primary power shuts down, the data backup circuit still works. However, there are two disadvantages using conventional retention register: when the number of retention registers is large, there will still be a relatively large standby power; the increased difficulty of placement and routing, because of the consideration of backup power supply and Always-On cells for Always-On signals.With the development of Non-Volatile Memory, NVM-based register can be used to backup data up when power down, because NVM has the ability to main data when power down. In all kinds of NVMs, Spin-Torque-Transfer Magnetic Tunnel Junction has being the focus of many researchers because of its non-valibility, unlimited write times, CMOS compatibility, no area overhead, and good scalability. This paper do a systematic research on STT-MTJ, writing and reading circuit of STT-MTJ, and registers using STT-MTJ. The major work of the paper is as follows:(1) Modeling of STT-MTJ: based on the physical equations of STT-MTJ, including resistance, critical current, switching condition and thermal fluctuation equations, a compact model of STT-MTJ is presented. The model uses Verilog-A language and can be co-simulated with standard CMOS circuit. Then, the model is simulated using HSPICE.(2) Study on writing circuit of STT-MTJ: the relationship between switching power and driving strength, between writing delay and driving strength has been analyzed. The choice of driving strength in a STT-MTJ register has been discussed.(3) Study on reading circuit of STT-MTJ: the relationship between the width of sensing NMOS and sensing delay, between the width of sensing NMOS and reading disturbance has been analyzed. The sensibility of electron charge in reading circuit has been analyzed. After that, things to be cared about when sensing data is to output is pointed out.(4) Design of STT-MTJ based retention register: conventional STT-MTJ register is analyzed, and its disadvantages such as low speed and high power dissipation are pointed out. Existing STT-MTJ retention register and its disadvantage of data override are analyzed. Based on the studies mentioned above, saying the STT-MTJ model, the writing and reading circuit of STT-MTJ, a new retention register using STT-MTJ is presented. It separates STT-MTJ from both master and slave, divide the working mode of the register, so that the speed of the register is increased and average power of the register is reduced. Besides, it overcomes the data override problem in existing STT-MTJ retention register. For example, if the retention register is in DFF mode90%of time, and in SAVE and RESTORE10%of time, then the speed increases by15.2times, average power reduces by89.4, while the area increases only12.5%.