SOPC Design And Implementation Of Speech Denoising Algorithm

In the processing of speech signal, the speech processing can be influenced by interfering noise, and speech processing system’s performance will be a sharp decline. To solve this problem, speech denoising algorithms can extract pure speech from noisy speech as much as possible, improve signal-to-noise ratio (SNR), and have an important significance in the field of speech signal.Through consulting a great number of relevant references at home and abroad, it is summarized that, traditional methods of speech denoising such as wavelet transforms (WTs), filtration algorithm, have obvious effects for specific noise, and poor self-adaptive. And most algorithms focus on the theoretical research, are time-consuming, and have not been implemented on hardware platform. So, this paper proposes two design projects of speech denoising algorithm, which are based on Empirical Mode Decomposition (EMD) and Fast Independent Component Correlation Algorithm (FastICA) separately, and be programmed to implement on FPGA platform. The main tasks in this paper are:In the aspect of algorithm simulation, firstly, EMD and FastICA algorithms are simulated in MATLAB development environment, the TIMIT speech library and Noise-92noise library are used as test set, pure speech and noise signal are mixed with different SNRs. Through results of processing mixed signal, the algorithms’ correctness is verified.In the aspect of algorithm implementation, FastICA algorithm is implemented by using Verilog hardware description language in Quartus development environment and timing simulation in modelsim environment is verified by using standard test set. FastICA is packaged into IP core, and added to SOPC framework. EMD algorithm is implemented by using C language in NIOS Ⅱ IDE environment, and float customized instruction set is used to accelerate with regard to time-consuming steps.In the aspect of system implementation, NIOS Ⅱ processor is adopted as the core of control and MIC interface is used to collect speech data, which will be mixed with noise data saved in on-chip ROM according to different SNRs. The mixed data is processed using EMD algorithm and FastICA algorithm separately, and speech wave is displayed on LTM. At last, the system is verified and implemented on Terasic DE2-115development platform.Throuh testing, it is proved that, this system has implemented function of speech denoising and achieved the design specifications. When the clock frequency is50MHz, the time of processing speech data with the amount of8000, which uses FastICA algorithm, is10.08ms. EMD algorithm improves SNR9.36dB, and is superior to FastICA algorithm. The algorithms have wide range of applications in the fields of speech coding, speech recognition and so on.