Implementation Of FPGA Based JPEG Decoder For Wireless Capsule Endoscopy

Intubation endoscope, as the main traditional method for clinical diag-nosing digestive diseases, usually brings patients immense suffering. Intuba-tion endoscope always lacks the ability of the medical examination of thesmall intestine segment. Wireless capsule endoscopy could overcome thisshortage, by the revolutionary diagnosis method, which needs patients toswallow the electronic capsule for acquiring the image/video information allalong the digestive track, for discovering and analyzing the suspected lesions.Since the invention of first wireless capsule endoscopy by Given Imaging theIsrael medical company, technology of capsule endoscopy is still rapidly pro-gressing. While in both of the practical design and the clinical demand, thereare still many limitations exist in the capsule endoscopy, such as the lack ofthe control of the position and gesture of the in-vivo capsule, high possibilityof missing detection of lesions, low quality and fps of the wireless digitalgraphics, difficulty of precisely positioning the in-vivo capsule, etc.This design is to support the program of Magnet Controlled ElectronicCapsule for Clinical Diagnosis of Human Intestinal Track, which is sponsoredby the National Natural Science Foundation of China (NO.31271069). By us-ing an external magnet for interacting with the capsule inside the digestivetrack, doctors control the position and gesture of the capsule to decrease thepossibility of miss-detection. This design proposes the concept of controllable,visible and scalable platform for integrating tools for micro operation anddrug release. This design focuses on the subsystem of the digital image com- pression and transmission. A lot works are completed in the design, simula-tion and verification of the Baseline JPEG compressor. This thesis systemati-cally discussed the Baseline JPEG algorithm, and all the details of keysub-modules design, including the color space transformer, thedown-sampler, the two-dimensional discrete cosine transformer, the quantiz-er, the run-length encoder, the variable-length encoder, and the Huffman en-coder. This thesis also describes the design of the Xilinx FPGA-based verifica-tion platform and the STM32–based wireless data receiver. By both of thesoftware simulation and FPGA verification, the experiment results show thatthe proposed Baseline JPEG compressor can work efficiently and stably underan approximately compression ratio of30:1. The typical PSNR value is guar-anteed to be higher than25dB under the compression ratio of40:1, which isconsidered to acceptable in the wireless applications. For images in size of320by240, the digital compression and transmission can reach32fps under a2Mbps wireless digital channel. This design completed the sub-system of dig-ital image compression and transmission, achieved the phased goal of modu-lar developing and verification, and laid the foundation of future works ofhardware integration and joint debugging on system level.