Design Of Digital Part Of RFID Tag Integrated With Temperature Sensor Based On EPC C1G2Protocol

Internet of Things is an intelligent, advanced, interconnected communicationsnetwork, known as the third wave of information following computer and internet. Asthe core of the Internet of Things, Radio Frequency Identification (RFID) is a kind oftechnology which uses electromagnetic induction or microwave with wireless andbidirectional communication. Sensors play an increasingly important role in daily lifeand make lifestyle more intelligent. The combination of RFID tags and sensors，forming the terminals of Internet of Things, will also be the future trend ofdevelopment. With the development of the Internet of Things, RFID technology willbe in large-scale application for the next few years.The main content of this article is to design digital parts used for the RFID tagintergrated with temperature sensor, which is based on static random access memory(SRAM). At first, this thesis designs the system structure of RFID tag and analyzesthe protocol. Then the system design, radio frequency and analog modules，sensorsare introduced. Finally, this thesis focuses on the completion of SRAM, digitalbaseband, and physical implementation.According to the protocol and design,64×8bits of synchronous single-portSRAM is selected, and Memory Compiler is applied to produce the correspondingfiles with the support of process. At the same time, the produced files are convertedinto other needed files. Because this design is based on the previous project，most ofthe digital baseband parts have not been changed, so this article mainly introduces themodified parts in detail, such as the interface of SRAM and the module controllingsensor. The temperature information will be a part of ACK command reply. Physicalimplementation contains logic synthesis, formality check, Place&Route, sign-off andso forth. This paper mainly completes logic synthesis and Place&Route, and describesits process and theory. Meanwhile, formality check, static timing analysis (STA),post-simulation, physical check and power analysis are achieved, which are essentialmeans for sign-off. Pre-simulation and post-simulation are completed by Modelsimsoftware. FPGA verification is finished by FPGA of Cyclone II with adequateresources. The result of simulation and verification indicates that the goal of design isachieved. The digital part is processed in UMC0.18μm CMOS. The whole chip areawith IO is940×940μm2, and the SRAM area is210×210μm2.