Research And Design Of High-Resolution Incremental Sigma-Delta ADC

As the rapid development of signal processing systems, higher resolution of ADCis required. By using the oversampling and noise shaping technologies, Σ-Δ ADC canwell meet the demands of high-resolution ADCs, without limitation of the matchingaccuracy of analog circuits. Therefore, it is widely used in various fields. IncrementalΣ-Δ ADC is a kind of oversampling ADC, whose input signal frequency is rather low,and even DC voltage as an extreme case. It is mainly used in instrumentation andsensor measurement which is sensitive to offset error, INL and DNL. At the beginningof a new conversion, the integrator in the loop and the digital filter are both reset, inorder to eliminate the information remained from the last quantization. It can beconsidered to be a traditional Σ-Δ ADC working in transient mode.This paper researches the theory of incremental Σ-Δ ADC in detail, and deducedthe expression of quantization error from the time domain and frequency domain,respectively. According to the results of derivation, incremental Σ-Δ ADC can beextended to two different directions to acquire high resolution, which are residualerror quantization and high order modulator. The circuits of incremental Σ-Δ ADC iscommonly implemented with switch-capacitor, so this paper analyses the effect ofnon-idealities, including input signal noise, switch noise, integrator noise and clockjitter. In addition, a method for incremental Σ-Δ ADC to eliminate the offset error isproposed.This paper designed an ADC for battery monitoring chip, which is a second orderfeed-forward incremental Σ-Δ ADC. With5V supply voltage, the ADC need toachieve12Bit resolution, ranging from-0.3V to5V. The circuits of ADC weresimulated and verified in the VIS0.4um BCD process. And the layouts of thesecircuits were designed and post simulations had been done. The simulation resultsshown that the designed incremental Σ-Δ ADC could realize the demanding functionsand meet system requirements.