Research On Numerical Simulaton Of Multi-scale Structure In TSV Interposer Package

3D packaging is considered to be the mainstream of the development direction offuture packaging technology. TSV (Through Silicon Via) technology, which hasbecome the most promising packaging technology, plays a very important role inachieving the shortest, the most abundant in z direction interconnect in3D integrationtechnology. TSV interposer package is the most likely mass production of3Dpackaging.The reliability problems caused by the mismatch of thermal expansioncoefficients (CTE) of the materials inside TSV interposer packaging has become thebottleneck for massive production. There are large numbers of micro bumps andmicro solder balls, the size between entities in the package has a difference in3ordersof magnitude. This multi-scale structure brings difficulties in building the finiteelement model.This paper focuses on three layer structures, i.e., micro bump/underfill layer, TSVinterposer layer, micro solder/underfill layer, among which there exist multi-scaleproblems. Accordingly, three homogenization methods, were proposed to build threehomogenization models for above three layers, respectively.For the homogenization in each layer structure, there are four models, the wholemodel of the layer, the equivalent model based on homogenization method, thesubstitutive model of the major material(underfills, silicon) in each layer, and thesubstitutive model of the minor material(solder, copper) in each layer. An FEMsimulation was conducted to obtain the thermal fatigue life of solder joints. Bycomparing the BGA solder ball life between the last three equivalent models and thewhole model, the feasibility of the last three equivalent models are verified.After comparing the above three homogenization methods for calculating thethermal fatigue life of solder joints in3D TSV interposer board level packaging, it issuggested that the micro bump/underfill1layer and the micro solder/underfill2layercan be modeled using their own underfill layers, respectively. The TSV/interposerlayer can be modeled using silicon board in a finite element analysis of the thermalfatigue life of board-level solder joints. The said three equivalent models cansystematically solve the multi-scale problems in3D interposer packaging.