The Design And Simulation Of FPGA-based Baseband Signal Processor For Beidou Receiver

Along with the rapid development of Beidou (COMPASS) satellite navigation system, satellite navigation industry has been greatly developed. Beidou receiver is the user terminal equipment in the Beidou satellite navigation system. The low-cost and high-performance features of the receiver make it applied widely. The design of the Beidou receiver could be divided into three parts:RF front-end, baseband processing and positioning solution. In these parts, the performance of the baseband processing greatly determines the performance of the receiver. So, the research of baseband processing is an important part of the development of high-performance receiver. Baseband processing mainly accomplishes capture and tracking the satellite signal, which makes carrier frequency and pseudo-code phase between the interior carrier signal and intermediate frequency signal from RF front-end consistent. When tracking is in stable state, the satellite ephemeris and almanac data could be demodulated, and the pseudo range observation quantity and value of Doppler frequency shift could be extracted for calculating value of the PVT (position, velocity and time) in the part of the location decoding.In this thesis, the realization of Beidou receiver based on FPGA is studied The thesis also focuses on the research of capturing and tracking of the baseband processing. The capture of the Beidou satellite signal is three-dimensional search, which contains satellite number, carrier frequency and Pseudo-code phase. Common signal-capture method includes the time-based serial sliding correlation capture domain method, frequency of parallel search capture method, parallel code phase searching trapping method. This thesis analyses these three different capture algorithms in the computational complexity and capture time, and selects the time-based serial sliding related capture domain method to design the BD2satellite signal capture.The satellite signal tracking is divided into the carrier tracking and pseudo-code tracking. The COSTAS loop structure is usually used in carrier tracking and usually delay lock loop structure is usually used in pseudo-code tracking. In this thesis, the same structure is used in the design of carrier tracking and code tracking in BD2.The design of baseband processing is primarily verified in the Xilinx-based FPGA and ARM9hardware platforms. The VHDL language is used to design the core module of the baseband correlator. It is include the carrier NCO module, pseudo-code generator module and code NCO module. The design is simulated with Modelsim. The simulation results show the validity of the design.