A Density Balance-aware Partition Methodology Based On Graph Partitioning Program Metis

With the development of integrated circuit technology, NoC (Network on Chip) with low latency, low power consumption has become a new direction of SoC FPGA prototyping verification has become a hot research spot of NoC. Large-scale multi-core NoC verification cannot be achieved on single FPGA, as it needs to be divided into multiple FPGAs. This paper proposed a method based on Metis graph partitioning algorithm with multi-weight constraints aimed at multi-core NoC circuit partitioning problem and completed the testing and validation of the algorithm.Firstly we analyzed the key problems of partitioning, transmitted the circuit partitioning problem to the graph partitioning problem. And we also analyzed and compared various typical partitioning algorithms, summarized the basic design flow of dividing algorithms. As a key point, we analyzed the principles and workflow of Metis algorithm and raised an improved multi-weight constraints partitioning algorithm. Right before the division of the multi-value integration and assess the effect of the partitioning in order to modify the integration parameters to improve the balance of the various parts. Finally, several different multi-constraints graph have been used to verify the effectiveness of the algorithm. Simulation results showed that the proposed algorithm can effectively save FPGA resources and reduce costs.This paper presents a multi-weight graph partitioning algorithm based on Metis algorithm. As taking constraint conditions into account, it ensures the balance of partitioning. It offers a new solution of partitioning large scale NoC circuits.