The Research Of Automatic Placement Algorithm For Test Chip Design

As the semiconductor industry has entered the "More than More" era, the technology of IC manufacturing has become extremely complex, and ensuring the yield has become difficult too. In order to accomplish the job of monitoring the IC yield during manufacturing, several new solutions of test chip ware introduced. The thesis focused on the placement of test structures for addressable test chip and test chip based on product layout, explored the automatic solution of test chip design.The thesis has accomplished the following research work:1. After researching the placement of test structure in addressable test chip, a set of rules was summarized and expressed as multivariate inequalities, and the mathematical model based on linear programming was established and developed into an automatic placer which will help the designer finish the placement of test structure quickly and automatically.2. After researching the placement of test structure in test chip based on product layout, the problem was transformed into mathematical expression and the target of placement problem was quantified firstly, then an auto solution combined linear programming and greedy algorithm was developed to improve the efficiency of test chip design.