Key Techniques Research Of Dirty Paper Coding Implementation Based On GPGPU

Driven by the huge demand from the market, wireless communication hasexperienced a surge of research and practical activities recently. However, the shortageof spectrum resource arises gradually and how to improve spectral efficiency becomesan urgent task to researchers and commercial corporations. To address those problems,software defined radio (SDR) and cognitive radio (CR) were proposed. Dirty PaperCoding (DPC) is an efficient technique to improve spectrum efficiency and has beenwidely adopted by MIMO communication, cognitive radio and data hiding, etc.Practical DPC design has gained much attention and DPC is predicted to be animportant technology in future communication solutions.Most of the algorithms employed in current communication standards share somecommon features, e.g. unified data orientation, real-time updating and processingconsistency. These features make it suitable to be implemented on stream architecture.As a typical stream architecture implementation, compared with ASIC and FPGA,Graphic Process Unit provides low-cost, programmable and flexible solutions, whichhas become a very active research area lately. Pioneering works of DPC theories weredone by several research groups and many practical DPC designs were presented inrecent years. Based on the analysis of those works, three computational part of DPC wasextracted, e.g. decoding of Low Density Parity-Check (LDPC) codes and RepeatAccumulated (RA) codes and BCJR algorithm. Additionally, all of the three parts aresuitable to be parallelized and implemented on GPU.Based on pioneering works, the structures and decoding algorithms of LDPC andRA were analyzed, the method of transformation between parity-check matrix andinterleaver has been improved, and the parallelism of those decoding algorithm has beenexplored exhaustedly in this thesis. Based on the experience of GPU architecture, anoptimized multi-stage mapping strategy (OMMS) of LDPC and RA decoding isproposed and implemented from an architecture perspective. The performance isenhanced significantly by balancing the memory access and computation, optimizingexecution configuration and the memory access pattern and fully utilizing thehigh-speed on-chip resources. The proposed decoder can achieve383-x and442-xspeedup compared to CPU-based decoders, and15.2Mbps and23Mbps throughput forLDPC and RA code, respectively, and the achieved throughput is comparable toexisting GPU-based decoders, which verifies the high efficiency of the OMMS strategy.Moreover, GPU can achieve superior performance with longer codes, which coincideswith the requirement of DPC.