Researching And Customizing Of Interconnect RC Corner

With the development of integrated circuits being taken into nanometer process,interconnection has become the key factor of circuit performance instead of device.Because of the existence of process variations during manufacturing, the interconnectprocess parameters are deviating from design value after manufacturing. The analysismethod which based on process corner is an important method, and it’s an effectivemethod for analysis the VLSI’s timing under considering process variations. However,with the increase of operating conditions, the number of process corners is larger andlarger, which leads to the time of STA(Static Timing Analysis) is growing largely. Thispaper is focusing on this problem and researching on interconnect RC corners, andcustomizing a RC corner which can cover the other signoff corners. The main work andresearch result of this paper includes:Basing on the extraction of interconnect parasitic parameter and interconnectdelay model, we are analyzing the influence of interconnect process variation,and then researching on the interconnect process parameter of these5RCcorners deeply. And we get the5corners’ process parameters setting and theconnection of interconnect’ resistance and capacitance and interconnect delayamong the5corners by analysis and experiment.Designed the flow and method of custom RC corners. And we customized anew RC corner. And compiling scripts which are used to calculate thecorverage of violation paths among the different corners.Estimating the corverage of the custom corner and analyzing the derating ofworst slacks and violation paths with some modules. The result show that thecoverage of custom RC corner to the other corners up to99%, and the slack ofsingle timing path increased by0ps to30ps and the number of violation pathsincreased.Improving the traditional MMMC analysis flow with the custom RC corner.The result of application case in engineering show that the runtime of toolsreduced greatly at the cost of buffer count and buffer area. The buffer countincreased by22.07%and the buffer area increased by21.65%whereas theruntime of tools decreased by84%after the timing is closuring.The research mentioned above has resolved the problem that the time of toolsrunning hugly each STA, and got well progeny when were applied in the engineering.