Radar Signal Processing Algorithm Design And Implementation Based On FPGA

With the development of micro-electronics technology, digital signal processingbase on FPGA (Field Programmable Gate Array) has made rapid development,FPGA is increasingly replacing DSP as the front-end digital signal processing. Sowith radar signal processing as the background, we discussed the radar signalprocessing algorithm design and implementation based on FPGA.Based on the characteristics of FPGA, we designed a radix-4dual-butterfly pulsecompression processor with block floating-point in FPGA. The processor partitionsthe data into block and uses dual-butterfly computing parallelly. And the blockfloating-point arithmetic is applied to extend the dynamic range of the data.When using the phase-coded signal as radar transmitting signal and samplingeach sub-code two points, the pulse compression side-lobe has certain improvementwith the odd-point sequences and even-point sequences respectively compressing. Inthe implementation of a radar signal processor, we applied this method in FPGA.Therefore, this paper also discussed this method’s effects for pulse compression.In application, each radar transmitting signal form has advantages anddisadvantages: the linear frequency modulation signal is insensitive to Doppler, butthe distance-resolution, velocity-resolution and measurement accuracy are nothigh;the complementary codes autocorrelation side-lobe amplitude is equal andpolarity-opposite, pulse compression can get zero side-lobe after superposition, but itsDoppler tolerance is very poor, a low Doppler frequency-shift will cause increasedside-lobe seriously. Therefore, how to eliminate the modulation of Dopplerfrequency-shift in the pulse and achieve a side-lobe as low as possible is veryimportant in the phase-coded pulse compression. So this paper also analyzed aDoppler compensation method based on DMTD to support the implementation inFPGA in the future.