Parameterized IP Core Design And Implementation Of Vector Memory On The YHFT-matrix

With the development of computer architecture and integrated circuit technology, the frequency of microprocessor gets higher and higher and the increase of CPU computing power is far beyond the growth of memory performance.The performance difference between CPU and memory which is called "Memory Wall" has become the bottleneck to further improve the overall performance of microprocessors. Furthermore, in the vector processors applying for streaming media applications such as wireless communication and image processing etc, the Memory Wall problem becomes worse. How to provide much more flexible and efficient memory access approach for vector process units(VPU), exert the data processing ability of VPU, extend the application of vector processor and enhance the degree of integration on SOC are the keys to design high-performance DSP and enhance the competition of vector processor in chip market.YHFT-Matrix DSP developed by National University of Defense Technology is a high-performance vector processor for SDR(Software Defined Radio) application. Based on the architecture of YHFT-Matrix DSP and the characteristic of accessing algorithm which is applied in wireless communication field, this paper has put forward a set of vector memory access instructions and designed its large-capacity vector memory (VM). In order to improve the flexibility and efficiency of vetor data access, the VM could support vector condition access and multi-wide SIMD non-aligned vector access. The logic circuit of memory access pipeline in VM is realized, which includes decoding, address computation, arbitration,rewriting data alignment, data write back and so on. Based on these, according to the diversity application of YHFT-Matrix DSP IP, we have extracted design parameter and realized the SIMD width and the VM capacity parameterized design. The SIMD width parameter has four configure values that is2,4,8,16. The memory bank of VM capacity has two configure values that is16KB or64KB. Finally, we give VM IP core fully functional verification from module level to system level and logic synthesis. The experimental results have shown that the function of VM IP absolutely correct, completely meet the design requirements under different cases of parameters configuration. In45nm cmos process, its frequency can reach700MHz. So it can provide717Gbps vector,375Gbps DMA,45Gbps scalar memory access data which meet the requirement of data throughputs and bandwidth of VPU.