Design And Verify Of The Exception Handling Mechanism And Multi-thread Mechanism In FT-Matrix IP

With the rapid development of the SLSI and EDA instrument, the IP reusemethodology has become the first choice of the SoC design. It is a crucial technique forchip design to curtail engineering project design cycle, save the cost efficiently, reducethe risk and ensure the quality of item. Nowadays the IC industry more and more focuson the attention to IP research.In the application of3G/4G communication, image/video processing, radar signaldisposal etc, as the large data, high parallelism and real-time performance, it is a greatrequirement for exception handling and multi-thread mechanism to respond the dataspeedy in DSP.Based on the background of a high performance DSP（FT-Matrix）IP which ismainly used for wireless communication and image/video processing. this thesis designand verify the exception handling mechanism and multi-thread mechanism. The mainworks and contributions are as follows:According to the demand of the function in FT-Matrix IP, this dissertation give thefeatures of the exception handling mechanism and achieve the hardware circuit design.the function which includes exception nesting, exception priority handling etc. Becauseof the full executing process has been monitored, it is effectively to figure out thedifficult issue of the error orientation in the process of the program debugging.Taking on the character of the whole architecture in FT-Matrix IP, this paper putforward the scheme of the multi-thread mechanism and accomplish the project of thelogic design. the outcome indicates that not only does make the control logic simple butalso greatly increase the using ratio of the hardware in processor.By performing a mass of arithmetic and analyzing the performance and superiorityof the multi-thread mechanism.After finishing the responsible design of the FT-Matrix IP, I built the emulationverification environment and carry out the related to function verification and timingverification, the results display accurate and meet the desire. Meanwhile, under the65nm technology library, then making uses of the Synopsys tools to carry through thesynthesis and optimization, the system clock frequency can finally up to700MHz.Now the FT-Matrix IP has been successfully taped out. the final results of the chiptest display that the design of the exception handling mechanism and multi-threadmechanism meet the requirements and make a further advance of the performance.