The Research Of Main Algorithm For Portable ECG Monitor Based On FPGA

The ECG monitor is developing towards miniaturization, functional diversification and is required that has real-time analysis and diagnosis function. To achieve these functions, it is required that the processor has a high performance and powerful algorithm processing. Now, in the main processors and programmable chips, FPGA is the ideal choice.In this paper, we choose FPGA as hardware platform, and mainly study the ECG signal processing algorithms based on FPGA. Finally, a portable ECG monitor is designed to verify the rationality of the design method. Firstly, this paper introduces the structure and principle of FPGA and the Nios â…¡ soft core, compared with the traditional embedded system and the embedded system based on Nios â…¡, and then the FPGA realization methods of ECG signal processing algorithms are studied.The specific research works of this paper are as follows:1. We study mathematical morphology and CDF9/7 wavelet transform in the application of removing ECG baseline drift. Besides we carry on the research of CDF9/7 wavelet transform for removing high frequency noise in ECG signal, and compare the advantages and disadvantages of the two algorithms in terms of baseline drift. Research the mathematical morphology and difference method, which are used to detecting QRS wave. Propose FPGA implement methods of the three algorithms, and carries on the simulation and verify the rationality of the design methods.2. According to the hardware and software design theory, we present the implementation scheme of system hardware based on Nios â…¡ soft core and the FPGA hardware circuit, and design the Quartus â…¡ schematic diagram of the system. In the design of the system, the method that the CDF9/7 wavelet transform and morphological filter are combined is used to remove ECG high frequency noise and baseline drift. This method is achieved good results in the filtering effect, resource consumption, calculation complexity and efficiency. Finally, the software designs are completed, which control peripheral circuit of FPGA chip and Nios â…¡ system connection and communication.At last, the testing and analysis of the overall design are conducted, and verify effectiveness of algorithm and the rationality of the system scheme.