The Research And Implementation Of Synchronous Sampling Methods And Electrical Parameter Detection Based On Power Quality Analyzer Implementation Of Handheld

With the rapid development of economy and technology in our country, various nonlinear and impact load connected to the electricity grid in great quantities may cause the rising number of factors which affects the power quality, and power quality problems gradually attracted wide public concern. According to the power quality standards, the use of testing technology as much as possible to undistorted access to grid signal important information, through real-time and accurately measure the power parameters detection algorithm related to power quality parameters, providing complete power quality related data, is of great significance to the problem of power quality regulation and governance of power system.However, it involves two difficult problems to be broken through and solved. One is how to effectively obtain as far as possible the real original signal of the grid signal. The other is how to obtain the basic information accurately and quickly calculate the relevant power quality parameters.For the first major problem, considering asynchronous sampling needs much more data, more complex algorithm and not good precision, so it is not too suitable for the real-time measurement of multiple parameters. Therefore, in this paper synchronous sampling is selected as a basic way to the information of original grid signal, and two kinds of synchronization methods with high precision and relatively simple implementation are studied, which are as follows:In view of the traditional digital phase locked loop is usually with the relatively narrow capture range, not strong commonality and the difficult balance between lock time and system stability, in this paper an advanced digital phase- locked loop has been designed. This digital phase- locked loop uses PI control to realize the digital loop filter, and the use of adjustment module with the function of adaptive parameter makes PI control parameters and the center frequency of the numerical control oscillator can dynamic adjust phase lock loop in fast acquisition phase, phase transition and slow catching coordination and switch between three different working state in order to achieve wider capture range, faster locking time and better stability. The loop can lock the input signal in 1~8 cycles when its frequency is in 20Hz~ 48 kHz, Where the system clock is 50 MHz, with the synchronous error which is 200 ns.In this paper, another kind of synchronous sampling method is also provided. Referencing the thinking of traditional software synchronization method, and in order to overcome the software synchronization method of sampling interval error accumulation and dispersivity of the original rational interrupt response time problem, a new method based on FPGA hardware equivalent synchronous sampling is proposed, which makes the FPGA the platform, the dynamic extraction algorithm to reduce the accumulated error and through the form of digital circuit to achieve equivalent synchronous sampling,with the final error in one sampling cycle(1 /sf).In addition, for method one, there is no direct strict mathematical relationships between the performance and parameters. The parameters are selected rely on experience and constantly repeated debug. Also, the second method has certain limitations. Its accuracy is greatly dependent on the frequency sampling rate, and higher rate ADC device is generally needed to be chosen, so the appropriate methods of synchronous sampling should be selected based on the actual application situation.For the second major problem, based on the research results of synchronous sampling, in our paper the method based on FFT to calculate electrical parameters is selected, the non-integer power of 2 mixed base of FFT algorithm is studied, and for the problem of the large amount of calculation has made the improvement to greatly reduce the amount of calculation and guarantee the precision of the original algorithm, and use the highly parallel processing ability of the FPGA to design the implementation of an improved mixed-base FFT algorithm scheme. The calculation precision of the FPGA implementation scheme within 0.7% is demonstrated by the joint simulation of Modelsim and MATLAB.