Design For Digital Frequency Detection Circuit Of MEMS Resonant Accelerometer

Nowadays, the technology of accelerometer’s miniaturization and integration is becoming a hot issue in manyfields. In this paper, the MEMS resonant accelerometer is a new type of accelerometer. Compared with the traditional accelerometer, MEMSresonant accelerometer has the following advantages: small size, stability, high accuracy and high reliability.Based on the resonant accelerometer which is characterized by a unique differential output frequency, accelerometer has high precision measurement whether work in static or dynamic state. Weresearch and design a high precision real-time frequency detection circuit, and design a processingcircuit for compensating digital detection signal. This paper can be divided into the following sections:Circuit Design section of this article mainly includes three modules: initial analog frequency signal test module, digital signal algorithms processing module and real-timefrequency output module. Analog frequency measurement module uses time sequence identification network and FPGA-based high-precision sampling compensation circuit. Digital signal processing module use LMS algorithm for data calculation and compensation.Considering of logic resource usage and speed of data processing, UART communication based on the FPGA is implemented to display output frequency.Matlab software build the algorithm model to identify indicators: the center frequency of system is 25 KHz, detection range is10 KHz, update period is under 200 ms, frequency resolution is up to 1×10-3 Hz, sampling depth of LMS algorithm is 216 and accuracy is4×10-8. We use Quartus II IP core and Verilogtocomplete design and use Modelsim and Quartus II to confirm the correctness of function.To achieve the desired design features, System is constructed by FPGA, including user-defined IP core and hardware platform using Verilog language. Finally, use ASK2C8 board to verify functional and timing simulation. The result shows the error magnitude meet the design requirement, less than 0.001 Hz.