Research On Application-specific Integrated Measurement And Control Circuits For Navigation-Grade Silicon Resonant Accelerometers

Silicon Resonant Accelerometers(SRA)are promising candidates instead of tradi-tional quartz vibration accelerometers and the mechanical servo accelerometers in small-sized navigation grade inertial system.However,this category of accelerometer has not been well studied.As a result,the bias instability of the accelerometer which affects the long-term navigation accuracy still have a long distance to that of its traditional competitors.This thesis will propose novel architectures of readout circuits and systems based on the analysis of noise mechanics,to improve the comprehensive performance of the SRA in order to shorten the distance between its performance and the requirements of high performance navigation.In order to provide principle guidelines for high performance sensors design,a phase noise model is proposed for SRA,which can be used to estimate frequency noise from the accelerometer.This chapter gives a unified approach to decompose the physical system into phase and amplitude modulation paths to predict the phase noise based on the characteristics of SRA.In this approach,the analysis for original nonlinear time-variant system can be symplified by analyzing several related linear time-invariant(LTI)system instead without degrading the precision.Furthermore,the model also reveals the relationships between mechanical displacement amplitude and design specifications,which can serve as guidelines for performance optimization.The soundness of this model has been validated against both time-domain numerical simulations and experimental results.This model is also applicable in microelectromechanical-system(MEMS)oscillators and MEMS oscillator based sensors.Second,this thesis proposes a novel architecture of CMOS readout circuit in SRA based on phase-lock loop(PLL).Which employs PLL instead of traditional AAC circuit to sustain the oscillation.This new architecture can lower the bias-instability of SRA without reducing the resolution or the acceleration noise density.As the high-performance frequency-to-digital converter which is proposed in the following chapter is also based on PLL,the combination of the FDC with the PLL based readout circuit can achieve better noise performance with digital output.Moreover,this new architecture can achieve low power consumption.Third,as navigation grade accelerometers set critical requirement on its resolution,and it is still difficult to meet this requirement by existing frequency to digital conver-sion techniques.The following chapter proposes a new sigma-delta frequency-to-digital converter(FDC)based on a PLL and a reset-counter.The reset-counter is inserted in the feedback path of a conventional PLL to quantize the phase and calculate the fre-quency.As PLL can boost the noise shaping effect from reset-counter,the quantization noise in low frequency region can be further suppressed.After implementation,this FDC can achieve high resolution under limited clock frequency,which release the trade-off between power consumption and performance in FDC.As a result,this FDC is suitable to be employed into high performance silicon oscillating sensors.Last,this thesis elaborates the implementation of a high performance MEMS-ASIC prototype of SRA,in which the MEMS sensor and readout circuit are fabricated in 80?m SOI and standard 0.35 ?m CMOS process,respectively.The SRA achieves 0.23?g bias instability and 1?g/(?)acceleration noise density with ±30g full-scale,which are equivalent to 4 ppb relative instability and 17 ppb/(?)relative noise density.In addition,this acceleromter achieves 1 ?g(?)resolution within 20Hz bandwidth,and 8?g/(?)resolution within 80Hz bandwidth.Finally,it only consumes 2.7 mW under a 1.5 V supply.The comprehensive performance has achieved the state-of-the-art performance.