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Design And Implementation Of A Noise Signal Acquisition And Compression Device With Memory Function

Posted on:2017-03-30Degree:MasterType:Thesis
Country:ChinaCandidate:A X CaoFull Text:PDF
GTID:2272330485489327Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
With the improvement of space telemetry system, there are more and more types of measurement parameter and the data quantity is bigger and bigger, which is a great challenge to the data transmission capability of telemetry wireless channel. According to research and analysis, the information redundancy of telemetry parameters is as high as 95%.Therefore, when the telemetry data is transmitted or stored, the redundant information can be removed first, thus greatly improving the efficiency of transmission and storage. In this paper, a kind of noise signal compression device with memory function is designed for the telemetry system of some launch vehicle, which can acquire four-channel noise signal in real time. Noise signal is one of the instant parameters of telemetry system, which has an important influence on the mechanical properties of the rocket body.Based on the characteristics of noise signal, this paper uses arithmetic encoding algorithm for data compression and the data packet length is 2048 bytes. The whole device is composed of three parts: the main control board, the storage board and the power supply board. The main control board uses a dual controller architecture based on FPGA+DSP, the main functions include four channel noise signal acquisition, data compression, data storage and data transmission. The storage board is connected with the main control board through a high temperature wire to store and recover the data, special anti-impact protection is carried out when the package is encapsulated. Data stream is the main line of the paper and we introduce the hardware design and logic design of the module flowed; according to the data stream transmission between the modules in the rate matching problem, we designed the buffer modules; the default initial value, cleverly designed multiple quantitative data in DSP of scheduling; using multi-channel buffered serial port to slow down the data transmission rate and to ensure the reliability of transmission; when record the data stream, we use the interleave two-plane program pattern, to the greatest extent improve the write speed.At the end of this paper, the test plan of the device are introduced. The results show that the system achieves the expected function and reliability requirements.
Keywords/Search Tags:Information redundancy, Noise signal, Lossless compression, FPGA, DSP
PDF Full Text Request
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