The Design Of LDO With Two VCCS And UGCC Compensation Schemes

Nowadays, with the prevalence of smart phones, PADs, laptops and digital cameras, there have been increasing demands for the portability and battery endurance of the electrQnic products. Because of the small volume of electronic products, the capacity of battery for them is small. In order to improve the power conversion efficiency, so as to increase the battery endurance, the power management technology is needed. LDO (Low Dropout Linear Regulator) is valuable in the field of application, with its market share of power management products up to 26%.Compared to other linear regulators, LDO can improve the power conversion efficiency. However, there exists a stability problem because of the variable output impedance of LDO with the change of load environment. In order to achieve the stability of LDO, much attention has been paid to the frequency compensation scheme of LDO.This paper studies the basic structure and theory of LDO. Several different frequency compensation schemes are analyzed and compared, and finally the two of them are selected:VCCS (Voltage Control Current Source) and UGCC (United Gain Compensation Cell). LDO with VCCS makes the frequency compensation with a small on chip capacitor of lpF, while LDO with UGCC can be used in low supply voltage applications.Seven LDOs are implemented in this paper. Each of them has four different outputs. They are designed and implemented on GF 2P4M 0.35μm CMOS process in this dissertation with a ceramic off-chip output capacitance of 4.7μF.Experimental results show that LDO using the two compensation schemes remain stable when the load changes from small current to the maximum load current of 300mA. At the output voltage of 1.2V, the variation amount of output voltage of LDO with VCCS is less than 30mV, when the load current changes from 1 to 300mA or 300 to 1mA with the rise and fall time of 100ns. At the output voltage of 2.7V, the variation amount of output voltage of LDO with UGCC is less than 60mV, when the load current changes from 1 to 300mA or 300 to 1mA with the rise and fall time of 100ns. Loop bandwidth of LDO can reach 2MHz at the maximum load current, and the settling time of LDO is less than 5ns. Dropout voltage of LDO can reach 150mV, and power supply rejection ratio of LDO is greater than 45dB within 0.001-40 KHz.