Design Of ARINC659Bus Testing And Simulating System

Along with the increasingly complex space missions, in order to deal with more and moremeasurement and control or loading, a higher requirement is put forward for on-board computers’security, real-time performance and reliability. Traditional structure of on-board computer cannotmeet the demand of the task. For solving the problem, a new Inner-bus is urgently needed.Since it has high reliability, fault tolerance and real-time performance, ARINC659is a buswidely used in avionics system. Due to the high cost and without reinforcement against radiationof domestic ARINC659chips, its application and development was limited. The FPGA design notonly reduces the size and stability of the circuit, but also shortening the debugging cycle of thesystem design, improving the flexibility of the electronic system design.This paper uses Verilog HDL to design the IP core of ARINC659bus is based onprogrammable logic devices. This IP core integrated with DW8051module, bus interface unitmodule, TM module, IMM module based on SOC technology, in accordance with the function ofthe bus protocol. In order to avoid single event upset in FPGAs in avionic applications, Thesystem joined with the EDAC modules, further enhancing the fault tolerance performance.The buscontroller integrated with a variety of common peripheral interface of on-board computer, settingup a variety of work mode, can be used in a variety of occasions.This design builds the bus simulation model, through the table driven proportional access andDW8051processor,the ARINC659bus controller produces the bus communicationwaveform.The model completed the ARINC659bus controller of normal functions such as datamessaging. By the meas of fault injection,the model verified the redundancy switching and thejudgment of data channel failure in ARINC659bus controller.The IP core ensured the faulttolerance and integrity of the bus communication.This paper researches the ARINC659backplane transceiver logic in the aspect of hardware.Its design from the load,the ability to drive and the transmission and so on to optimize thebackplane transceiver,ensuring the integrity of the high speed signal. At the same time this designset the FPGA verification platform of ARINC659chip.It verify the integrated FPGA logic on theverification platform. The test results show that the system works safely and reliably and it hasstrong ability of fault handing and shielding. Finally this paper studies the on-board computer architecture based on ARINC659form theconfigurability and back-end of system. There are also obvious advantages compared withtraditional master-slave parallel architecture.