Research On Process Layer Fault Simulator Of Digital Substation

With the development of computer technology、fiber-optic technology microelectronics and photovoltaic technology, the digital substation technology based on IEC61850communication protocol standard system is widely used in power systems, information transmission media at substation secondary side、information model、protection devices operation mode and many other great changes, the traditional testing methods and protection devices testing tools have been unable to meet the needs of the development of digital substation protection, especially in its process layer fault protection system testing needs.On the basis of in-depth analysis of digital substation three-tier structure and the content and features of IEC61850communication protocol standards, as well as GTNET_SV samples board transmission model in RTDS and GTNET_GSE board GOOSE transmission model built, configuration methods for protection devices built on the closed-loop real-time test platform, and proposes a plan that a process layer fault simulation device can be connected to the platform, enabling co-simulation of power system failures and process layer failures.In the design of the device, the network transmission delay should be reduced as much as possible in order to meet the requirements of processing speed and sending-receiving speed. Besides, the model for EP3C25QC8N FPGA chip is used as the central controller and88E1111chip with three-speed Gigabit Ethernet physical IP nuclear is used as an Ethernet module. To achieve the fault-simulating function of the device, the ’intercept-modify-forward’ failure circuit has been devised in the paper on the basis of the hardware mentioned. This paper also study the method of detecting the fault of information entropy and the fault-detecting circuit of power system has been devised on the base of this principle. To complete the two circuits’operation and realize the setting of fault, mixed-fault circuit is designed in the end.For the connection mode of fault simulator, this paper adopted the concatenated method and bypass method. The bypass method make devices have the ability to intercept at the same time and process muti-channels, which can realize the joint test of multiple relay protection devices. Finally, the performance of the device has been tested through the packet delay test and the test of detecting the fault of information entropy, proving that it can well meet the requirements for real time closed-loop test of the relay protection device in the digital substation.