The Research On Phased Array Ultrasonic Testing Equipment Based On FPGA

Ultrasonic phased array inspection technology(UPA) is an advanced ultrasonic nondestructive testing technology, by phase controlling each array element of array transducer, acquired the flexible and controllable composite beam, and dynamically controlled the position of focal point, has dynamic focusing, electronic scan and other features. Phased array inspection technology has become a hot research topic in the field of nondestructive testing, ful y digital phased array system is the direction of the future.FPGA due to the high integration and strong logic function, has gradually become the mainstream direction of digital phased array system is built. This study is based on the FPGA of ultraso nic phased array testing system. the main research content is phase control high precision launch problem, digital signal receiving problem and High-speed digital signal transmission problem.First, the theoretical analysis of the launch precision is carried out. To improve the resolution of the system, the accuracy of the delay control must be increased. The CPLD and the high voltage digital pulse generator MAX4940 are chosen to improve the delay precision. Dynamic focusing, dynamic aperture, dynamic apodization and digital beam formation kinds of phased receiver technology were analyzed theoretically. The stability of digital beam formation is better and the accuracy is higher.it can improve the quality of synthesis. So the formation of digital acoustic beam forming technology co nstitutes the receiving system. FPGA internal use of parallel processing technology and pipeline technology can easily achieve multi beam synthesis, so select the FPGA as the master controller for the phased receiver. Use PCIE interface to improve data transmission rate.Second, the composition and key module of ultrasonic phased array detection system are designed, launch part’s arrays are formed by multiple independent piezoelectric chips, through the PC software set the timing after CPLD controlled inspire each chip unit, controlled the focus position and scan direction of launch beam. Receiving part controlled each chip functions by the SPI interface, signal by the voltage isolation, amplification, filter processed and converted to LVDS signal into FPGA. Controlled by FPGA, data via PCIE interface into the upper machine, the final data by PC to deal with and analysis.Last, the various parts are simulated and the measured: measured the actual voltage of power supply, verified the simulation of launch timing, measured the pulse of launch part, verified based on the FPGA the simulation of receiving part SPI interface, measured receiving part’s the function of amplifying, filtering, measured the high-speed transmission of PCIE interface.The result: in the launch part, the most narrow pulse width can be up to 25 ns, The delay precision can be up to 130 ns, the highest can support transducer of the dominant frequency 20 MHZ, launching voltage is 300 V. In the receiving part, to test 80 installed base collection of 10 MHZ sine wave, can output better waveform. In the PCIE transmission parts, under single TLP different content of reading transmission rate can be up to 12 GBPS in steady state. The results meet the needs of the system, in order to the miniaturization and digital of ultrasonic phased array inspection equipment and high speed of data transmission provided the reference, and to the optimization of ultrasonic phased array inspection equipment is of great significance.