The Research Of Reliability Of InAlN/AlN/GaN Heterostructure Field-effect Transistors

GaN-based materials are promising candidates in high temperature, high voltage, microwave, and high power applications due to their wide band gap, high breakdown electric field, high electron saturated velocity and excellent chemical stability. Nowadays, GaN-based HFETs have been highly developed, however the device performances on high frequency and high power are still hindered by current collapse and device reliability. InAlN/GaN material system offers a highly attractive alternative for high-frequency, high-power applications. The InAIN alloy at an indium content of17%can be synthesized lattice matched to GaN and sheet charge density roughly twice that of typical AlGaN/GaN HFETs. This high sheet charge density is due to the more than4×increase in spontaneous polarization of In0.17A10.83N/GaN as compared to a traditional A10.2Ga0.8N/GaN heterostructure. These properties can be exploited to fabricate InAlN/GaN HFETs with very high current density, low access resistance, aggressive scaling, and monolithic integration of normally on and normally off operation, and even the possibility of taking place of AlGaN/GaN. However, in spite of those attractive advantages and broad prospects in high temperature, high frequency and high power applications, the reliability problems of GaN-based HFETs are not well resolved, which blocks the large-scale commercial applications of GaN-based HFETs and the replace of Si-based devices. It is concerning the problems of device reliability that in this thesis I have done some researches on InAlN/AlN/GaN heterostructures and devices, and got some important results, as listed below.1. Research of the strain of the barrier layer in InAIN/AIN/GaN HFETs. The strain is directly related to the converse piezoelectric effect and is one of important factors leading to device reliability problems. Theoretically, the InAIN barrier layer of In0.17A10.83N/AlN/GaN heterostructures is of no strain, which has, however, not been verified in actual heterostructure materials or devices. We introduce a method to calculate the strain of the InAlN barrier layer under the gate of InAlN/AlN/GaN HFETs, and then employ this method to investigate the strain of the barrier layer under the gate of InAlN/AlN/GaN HFETs with normal Ohmic contacts and side-Ohmic contacts. It is found that the InAlN barrier layers of those HFETs with different Ohmic contact processes are all considerately and compressively strained, and the2DEG sheet charge density under zero gate bias decreases with the increasing strain of the InAlN barrier layer. It is also found that the diffusing of Ohmic contact metal atoms into the barrier layer is a significant reason for the presence of strain in the InAlN barrier layer. However, there exist other reasons and further investigations are needed to draw a solid conclusion about the strain of the InAlN barrier layer and its regularity of distribution between the source and gate.2. Research of the interface trap states in InAlN/AlN/GaN heterostructures. Trap states in the GaN-based heterostructure materials can lead to current collapse and induce device reliability problems. In this thesis the conductance method is used to study the characteristics of trap states at the InAlN/GaN interface of InAlN/AlN/GaN heterostructures. The interface trap state density and time constant are extracted, which are (0.96～3.36)×1013cm-2eV-1and (0.29～1.61)μs, respectively. It is found that at biases in the vicinity of threshold voltage, interface trap states dominate the dispersion of C-V curves while surface trap states can be neglected. The relationship between the time constant of interface trap states and external biases indicates that among the interface trap states, those with higher energy level usually have shorter time constant for the trapping/de-trapping process. At last, the strain of the InAlN barrier layer is calculated to tentatively explain such high interface trap state density in InAlN/AlN/GaN heterostructures.3. Research of the degradation of InAlN/AlN/GaN HFETs. Experiments of electric property degradation are performed on InAlN/AIN/GaN HFETs. Drain-source current decreases are observed during I-V curve measurements and under long-time electric stresses, which are attributed to the buildup of hot phonons induced by hot electrons in the2DEG channel. The presence of large amount of hot phonons in the2DEG channel scatters the2DEG, decreases the mobility of electrons in the channel, increases the channel resistance and finally leads to drain-source current decrease.