The Design And Implementation Of Memory Management System In GPU

With the rapid development of semiconductor technology, and the emergence of the frequency wall, power wall, memory wall, Single-core processor has appeared to be inadequate for large-scale data-parallel computation. Graphic Processing Unit (GPU) changes its co-processor role gradually to a specialized large scale system chip for processing graphics data. For large-scale parallel computing, the GPU’s computation ability is far beyond CPU’s. Mainly thanks to its large number of computing units and high-speed memory bandwidth. Therefore, the graphic&image data access bandwidth directly determines the performance of graphics processor.According to making a detailed research and analysis of traditional GPU architecture and memory management system, this paper proposes a memory management system with hardware method for satisfying the requirements of accessing data efficiently when Heterogeneous Multi-core Graphic Processor Unit (HMGPU) rendering in real-time and parallel.Firstly, giving a detailed analysis about the specification of OpenGL1.3of HMGPU programming model, getting the result that data of texture image, fixed-loading program, buffer object and display-list need to be stored in the memory system of HMGPU. Texture image and fixed-loading program have regular properties but buffer object and display-list data changed with the application. Taking the space utilization and the simplicity of the design into account, this paper has partitioned the memory into two parts which is called fixed part and paging part. Fixed part manages the big-continuous data and paging part manages the small non-continuous data. In the meantime, according to the detailed operation style of HMGPU’s data management, concluding the outer interface of memory management system, and designing the memory management system of GPU. The memory management system is designed and simulated in HDL, and building the simulation platform with System Verilog language which comparing the result automatically. This method has improved the efficiency of simulation and saving the simulation time. And at last, it is verified to be valid in Xilinx DNV6_F2PCIE FPGA board. Results show that the memory management system works well and satisfies the accessing requirement of real-time parallel shading of HMGPU.