A Flexible And Configurable HW/SW Architecture For Image Processing

With the development of the technology, digital image information is various and widely used in almost every field, such as civil, military and commercial, etc., then the digital image processing technology is becoming one of the rapidly growing disciplines. Currently there are five implementation of image processing technology: pure software, DSP, simple image processing microcontroller, ASIC and FPGA image processing implementations. At the same time, integrated circuits technology is improving quickly and IP-based SoC design can shorten the period of development in a great range, so it is significant and practical to develop an image processing accelerator IP. To meet the requirements of real-time, high-speed and flexibility in high qualified and complex image information, we proposed a flexible and configurable hardware/software co-design image processing architecture which is based on accelerator.In this paper, with analyzing entropy coding, DCT (discrete cosine transform), color space conversion and image interpolation, we extract the basic arithmetic operations in complex computation and frequent calling process; based on those operations we design a flexible and configurable image processing accelerator. This accelerator has four assembly line to achieve the parallel computing. It supports the vector addition, vector multiplication, vector multiply-accumulate, shift, saturation and other basic operations. The way of hardware/software co-work in a specific image processing is to use the CPU to configure the task flow architecture flexibly in software, and call the accelerator to do the complex image processing steps. It can improve processing speed and frequency while reducing processor overhead.The design in this paper is based on the series of CK processors and CKSoC integrate tools which meets IP-XACT package standard, and they are belonging to Hangzhou Zhongtian Microsystems Inc. Then design the XML files and IP generator to integrate the image processing accelerator into CKSoC platform. CkSoC can configure the parameters of image processing accelerators flexibly to enhance the portability in various SoC design environment and achieved the efficient of accelerator configuration and integration. Finally, we use CkSoC to generate a simple JPEG image decoding system and driving the hardware accelerator to complete IDCT, inverse quantization and color space conversion while use the processor to do the other part with software, the final decoded image is displayed on the LCD monitor in FPGA. All the image processing based on this accelerator is in the way that:analyzing the image processing algorithm to divide the hardware and software architecture; driving the accelerator to do the complex arithmetic part; using the processor to do the control part. This method accelerates the process of image processing, while maintaining the flexibility of accelerator.