The Design Of RSA Algorithm And Implementation Against Power Analysis

Power analysis technology is an efficient side-channel attack, which is widelyused to corrupt cryptographic implementations. As there is a relationship betweenpower consumptions and instructions of cryptographic implementation, adversary caninfer private key or some other important information by observing powerconsumptions. Power analysis is easy and effective. In order to resist power analysisattack, principal method is to decrease or eliminate correlation between powerconsumptions and instructions in the aspect of hardware structure or cryptographicalgorithm.RSA is a famous, secure and useable asymmetric cryptographic algorithm, whichbase on big number factorization problems. It is usually used to encrypt/decryptmessage and signature in security system. However, in naive RSA hardwareimplementations, power analysis can crack key successfully because of strongcorrelation between power consumptions and instructions.In this paper, a new RSA hardware implementation is proposed to resist poweranalysis and safe-error attack. We implement the new RSA algorithm by GSMC0.18μm logic cells, and verify its ability to resist power analysis attack. The corework of this paper are as follows:1. We using a new fake modular multiplication to construct a R-L modularexponentiation algorithm that contain symmetrical branch structure. Our experimentshows its ability to resist first order power analysis and safe-error attack.2. Analyzing and evaluating shows that a new MWR2MM arithmetic unit getshigher computing performance at the expense of chip area. The new arithmetic unitneeds more adders and selectors to execute pre-computation, which decreases delaybetween process elements from two periods to one period.3. A power analysis experimental platform is constructed that is useful toimplement cryptographic algorithm and analyze its performance. An exactlysimulation about the performance of a hardware implementation before its tape-out isquietly important to avoid failure.