Research And Simulated Implementation Of ICS Technology For WCDMA Wireless Digital Repeater

WCDMA communication network has been all over the world, repeater is selected as a priority of weak signal area and blind spot coverage in the network. In all of repeaters the wireless repeater is welcomed by its flexible installation and lower cost. But the co-channel interference between the transmitting and reciving antennas has restricted its performance to futher enhance. In this paper, ICS(Interference Cancel System) technology is implemented in WCDMA wireless repeater to combat co-channel interference and improve the quality of output signal.Adaptive interference cancellation algorithm of ICS technology was detailed, at the same time classic time domain and transform domain algorithm was proved and simulated, such as LMS algorithm, NLMS algorithm, RLS algorithm, WHT-LMS algorithm and FFT-LMS algorithm. By testing the FFT-LMS algorithm is the best practicable interference cancellation scheme,but fixed step size of the algorithm leads to greater volatility error in the steady-state period. In order to reduce the steady-state error, this paper introduces Sigmoid function which can automaticly adjust the step size and error memory factor which can avoid stopping search earlier, then variable step size FFT-LMS (VSSFFT-LMS) algorithm was proposed.In Matlab different algorithm was simulated, the result showed that repeater which used ICS technology, could get7dB relative gain better than-15dB the standard required in the same isolation. The proposed algorithm could make the output signal constellation amass significantly in7dB relative isolation. The EVM value is8.33%within17.5%, which was decreased by3.3percentage points than fixed step FFT-LMS algorithm. The algorithm has the advantage of fast convergence rate and small steady-state error. Additionally, the effect of filter length and gain was considered in algorithm stability and a two-stage gain repeater structure is proposed.Finaly, VSSFFT-LMS algorithm was designed on FPGA platform. The ICS Core’s clock adapted64times rate of sampling. Reusing Xilinx FPGA FFT IP Core could effectively reduce the resource consumption. Data buffering and cascade block could be realized by block RAM. The data getted from ChipScope presented the improved algorithm could achieve the co-channel interference elimination. The content of this paper on wireless repeater design has a great engineering value.