Study On The Algorithm Of Ics Wireless Digital Repeater Station And The Fpga Implementation

With the rapid development of Digital Terrestrial Broadcast (DTMB) industry and the number of Digital Television (DTV) users increased dramatically, extension the coverage of DTMB network becomes imperative. On-Channel Repeater (OCR) used in Signal Frequency Network (SFN) as a relay station can increase the coverage and reduce the blind area of signal, but there is a coupling between the transmitting and receiving antennas, and the coupling echo limits the working efficiency of the OCR, because the echo will be amplified again by OCR, which destroys the spectrum of the transmitted signal, even makes the system oscillate. In order to resolve this problem, it is necessary to use high-performance echo cancellation technology, so the Interference Cancel System (ICS) of OCR is produced.Based on DTMB standard, this dissertation elaborated three kinds of adaptive algorithm used in ICS of OCR to realize the echo cancellation functions, which are LMS algorithm, non-parametric variable step size (VSS) NLMS algorithm and CORDIC LMS algorithm. Among them, the non-parametric VSS-NLMS algorithm can solve the conflicting requirement of fast convergence and low misadjustment of the LMS algorithm and the CORDIC LMS algorithm can reduce the difficulty of hardware implement and save resources. In CORDIC LMS algorithm, to further reduce the implementation complexity, three parallel real CORDIC LMS algorithm is proposed to realize the complex CORDIC LMS algorithm;to compensate the out-band spectrum distortion, the pre-whitening filter is introduced in the system.Secondly, this dissertation studied the FPGA architecture of complex Direct-Form Delayed LMS (DF-DLMS) based on Systolic. Because the system resources are limited, this dissertation studied the structure of8-tap DF-DLMS algorithm firstly, then put forward the structure of16-tap DF-DLMS algorithm using twice reuse technology. Due to the complex DF-DLMS algorithm cannot leave complex multiplier, this dissertation added two pipelines in complex multiplier to shorten the length of critical path.Finally, after implementing the16-tap DF-DLMS algorithm on FPGA, this dissertation integrated it into the whole OCR system and tested the system, then analyzed the test results and proved the correctness of the proposed structure.