The Research Of Improvement&Hardware Implementation Of MAP-The High Speed Turbo Decoding Algorithm

Due to the recent of the communication and the computer technology in the information era, high-speed accurate data transmission is becoming a more and more popular research topic. The invention of the turbo code has ended the history of using the cut-off rate as the actual capacity of the channel. The research of the error control coding has then entered an entirely new stage. Because the error control performance highly depends on the design of the turbo decoder, the algorithm and architecture of turbo decoder are widely discussed in the recent boom of turbo code research.There’re two types of decode algorithm for turbo code:SOVA (as known as Soft-Output-Viterbi-Algorithm) and MAP (Maximum A posteriori Probability). SOVA algorithm is simpler comparing to the MAP algorithm, and it is also easy for hardware implementation. However the error control performance of SOVA is worse than MAP algorithm. The basic idea of MAP algorithm is to calculate the state measurement of all the transfer states on the encode trellis, and then calculate the likelihood ratio and the value of each bit. Because MAP algorithm will actually calculate all the transfer state in the encoder trellis, it is more accurate than the SOVA algorithm. There1re lots of recursive calculations in the MAP algorithm, and the hardware implementation of these recursive calculations are complicated, so it is very important to improve the MAP algorithm for hardware implementation.This dissertation has researched the Radix-4MAP algorithm and compared it with the Radix-2MAP algorithm. Radix-4MAP algorithm could save half of the memory costs for the same clock cycles, and using Radix-4architecture would decode2bit per cycle, which will double the decode efficiency. Radix-4architecture has more practical value in the hardware implementation.Based on the research, the dissertation has proposed an improved Radix-4MAP algorithm. It can provide more accurate result mean while reduce the loss of coding gain. The dissertation provided a novel "Offset-Add-Select-Compare-Offset" architecture for the recursive calculation of the state measurement. Comparing to the traditional "Add-Compare-Select-Offset" architecture, it can reduce the length of the critical path of the decoder, hence increase the maximum frequency of the decoder. The dissertation also provided a novel block decoding method. It can avoid the extra memory cost of the traditional MAP decoder architecture.At the end of the dissertation, the results of MATLAB simulation are provided for different types of MAP algorithm. The performance of error controlling will be compared. The results of Verilog synthesis of different architecture are also provided. The result will prove the advantage of the algorithm proposed I in this dissertation.