Study And Design Of Implantable Low-noise Analog Front-end With Ripple Reduction Loop

Biomedical chip is the core part of biomedical System, which has been widely used inmedical detection, medical monitoring and artificial prosthesis such as retinal prosthesis,artificial cochlea, etc. Since its high accuracy and anti-interference capability features,implantable biomedical acquisition has been a hot research area of medical and biologicalelectronics field. Analog front-end is a key module of the implantable biomedical chip since itis connected to the sensing electrode directly and its design has a great effect on acquisitionaccuracy and anti-interference capability of the biomedical signals.Aiming to the application of implantable biomedical acquisition system, this paperproposed an implantable low noise analog front-end, which includes preamplifier, switchedcapacitor filter, variable gain amplifier and current reference to extract and amplify thebiomedical signal effectively. According to small magnitude, low frequency, and beingeffected easily by circuit noise, especially low-frequency noise for the biomedical signals, theproposed preamplifier of this paper uses chopper modulation technique to shift the lowfrequency noise to the chopping frequency and filter out it by low pass filter. After usingchopper modulation technique, ripple will appear at the output of the amplifier if DC offsetexist, thus this paper proposed a modified ripple rejection loop (RRL) with currentdigital-to-analog converter (DAC). Besides suppressing the output ripple successfully, themodified RRL with current DAC can solve the problem of the quiescent point drift appearedin the previous RRL with current DAC,.To improve the performance of the proposed analog front-end, the other three modules ofthe analog front-end including the switched capacitor filter, the variable gain amplifier and thecurrent reference were also considered carefully.Finally, the circuit and layout of the proposed analog front-end using chopper modulationtechnique with modified RRL were designed successfully with Global Foundry180nmCMOS process. The post-layout-simulation results show that with a power supply of1.8V and60μA bias, the input-referred noise within0.1Hz-10KHz is low to2.6μVrms, four gains of46dB,52dB,60dB and66dB are available, a high CMRR of146dB and a high PSRR of108dB are obtained, demonstrating that the designed analog front-end chip meets the demandfor implantable biomedical signal acquisition very well.