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The Design Of ISP System And FOGA Hardware Implementation

Posted on:2015-01-04Degree:MasterType:Thesis
Country:ChinaCandidate:K FanFull Text:PDF
GTID:2268330425476155Subject:Image processing and digital chip design
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ABSTRACT:Cameras have been widespread in every family and street, which play an important role in various fields. ISP (Image Signal Processing) system, which is the core controlling unit of camera, is not perfect and is not able to adapt to special scenarios in harsh environments. In the result, ISP system hinders the access to acquire high-definition video (HD video) for camera. Meanwhile, the speed of ISP system needs to be improved especially for capturing high-resolution image and real-time applications. Therefore the purpose of this paper is to optimize and complete the ISP system and accelerate its speed.At first, every algorithm in ISP system is tested and optimized in order to improve the efficiency and result of camera. In particular, innovative methods are proposed for auto-exposure and high dynamic range image enhancement, which achieve better results. With respect to hardware implementation, we referred to a lot of optimization techniques and design strategies and explored some empirical approaches. The real-time ISP system was implemented in FPGA through sophisticate hardware design. By comparing existing algorithms and our algorithms, it can be observed that our ISP system is capable of better controlling camera and capturing video and image with better effect. Furthermore, whether normal or extreme bright/dark scenario, the camera can work well by equipping our ISP system.In this paper, a variety of methods of optimization and acceleration were introduced, which were applied to real-time FPGA platform for the first time. Experimental results showed that our ISP system achieved a stable and fast video capturing even in the cases of bad light environments or cases where the scenes transform frequently.
Keywords/Search Tags:ISP, auto exposure, auto white balance, high dynamic range, contrastenhancement, FPGA
PDF Full Text Request
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