Study On CMOL Cell Assignment By Using Pseudo-boolean Satisfiability

With the continuous development of integrated circuits, the scale of CMOS semiconductormanufacturing process is steadily decreasing. A22nm microprocessor has been producted by Intelin2012, and the scale will be10nm in2018. But, when the manufacturing process is shrinked to10nm may be the physical limitation, and it will bring many unprecedented challenges such as ofquantum mechanical effects and high manufacturing cost will be brought. If the original CMOSintegrated citcuit technology is not changed, and the development of the intergrated circuit will beno longer underfollow Moore’s Law. Therefore, a new kind of sutructure which employsnanotechnology and traditional CMOS manufacturing process and consists of nanowirecrossbar-based nano/CMOS hybrid circuit architecture, CMOS/nanowire/Molecular hybrid,namely CMOL has been proposed by K. K. Likharev research team. CMOL architecture not onlyretains the current mature CMOS manufacturing process, but also has high integration density, andit is considered to be one of the most promising alternative technologies to CMOS technology inthe future. Such as the development of CMOS VLSI design, the compute-aided design of CMOLis also an important role in CMOL design. In this paper, much attention has been paid to theCMOL cell assignment which is a key problem in CMOL based design. The research of this papermainly includes the following sections:1) Cell assignmet for defect-free CMOL circuit. The Boolean Satisfiability (SAT) method hasbeen employed for CMOL cell assignment. Unlike the proposed SAT based methods, whichproduct too huge number of clauses and big intermediate processing file to make the methods workefficiently, a novel SAT method using Pseudo-Boolean Satisfiability (PBS) is proposed to solvethe CMOL cell assignment problem. Comparing to the reported SAT-based methods, theexperimental results show that the proposed method can reduce the number of clauses, theintermediate processing file efficiently, and needs less the CPU time and memory, and can dealwith bigger circuits.2) Cell assignment for those CMOL circuits with high fan-outs and less connect domain. Byinserting buffers in the output of the nodes with high fan-outs on propose, the connect-domain ofthose nodes is enlarged. Futher, using the proposed PBS method and the nestlist with insrtingbuffers, the cell assignment of such CMOL circuits is completed. The experimental results showthe proposed method can work well especially for those circuits with complex connections.3) Cell assignment for defective CMOL circuit. By analying defect model, a defect-tolerantCMOL cell assignment method based on PBS is proposed which can avoid the defects during the cell assignment, and realizes a correct logic function in a defective CMOL circuit.