The Design And Analysis Of SoC Architecture Based On AXI Bus

With higher and higher degree of chip integration, The oldergeneration bus—AHB bus or ASB bus is difficult to meet the systemrequirement of high performance SoC. So the SoC architecture based onAXI bus is becoming the development trend of high performance SoC. Thethesis’s target is to provide a solution for the design of SoC architecturebased on AXI bus.Firstly, AXI bus is analyzed deeply and compared with AHB bus andAPB bus. the thesis solves the problem of distributing different IP to AXI、AHB or APB. The thesis provides a complete SoC design flow based onAXI bus, including the method of bandwidth analysis, system analysis,hardware partiton and so on.This thesis focuses on describing the designand analysis of AXI bus matrix, and designs several different architecturematrix，including multiple address/data channel,share address/data channeland hybrid channel.Then the thesis analyzes internal architecture of all akinds of AXI bus matrix, and summarizes the feature and applicatonscenario for different architecture of AXI bus matrix. The decoder andarbiter of bus matrix classified by the function，and the thesis has a designmethod for the arbiter and decoder. The thesis provids a completerealization method for bridges (axi2ahb、ahb2axi、axi2apb).A verification platform is build to verify AXI bus matrix, including aperformance analysis unit， with which the platform can count thebandwith，latency，access time automaticlly.The design mentioned in the thesis has been applied to a SoC chip ofhigh display DTV，and the SoC chip has been produced successfully andused in TV. Practice has proved that the design can meet the systemrequirement of SoC chip.The design methond and flow mentioned in thethesis is worth promoting.