Research On Synchronization Control For Wafer Stage And Reticle Stage Of Lithography

Step&scan lithography is the current mainstream integrated circuit manufacturingequipment. Its development involves optical, mechanical, precision measurement,control, so it is one of the most sophisticated equipments which manufacturingintegrated circuits. Synchronization control for wafer stage and reticle stage needs bythe technological development of lithography machine, and synchronization controlperformance directly affects lithography resolution and overlay accuracy， is a keytechnology of step&scan lithography.In this paper, considering synchronization control problem, from synchronizationcontrol strategy and synchronization control algorithm, first analyzing thecharacteristics of the cross-coupling and master-slave synchronization control strategyand synchronization control strategy adopted by ASML company. considering repeat-able action of the scanning exposure process, designing iterative learning control lawfor synchronization control algorithm, and theoretically proving the convergence ofiterative learning law.Synchronization control card is one of the core control boards of step&scanlithography, high-performance synchronization control card is nessesary to achieve highspeed processing and high-precision synchronization control. Therefore usinghigh-performance DSP and FPGA as the core device of synchronization control card,DSP with TI’s TMS320C6414the central processor, can achieve high-speed dataprocessing operations, FPGA using Altera’s EP2S60F1020access chips for the interface,in order to meet more kind of interface to access communication.Synchronization control card access through the FPGA for each interface,designing the appropriate interface logic modules. First planing overall block diagramof the interface logic to the FPGA dual-port RAM for the cache, connecting theinterface logic module and DSP EMIF interface logic module, and then designinginterface logic module by working principle, and carring out the actual test.In order to verify synchronization performance the proposed iterative learningcontrol algorithm. first designing the conventional PID controller, using the positionloop, velocity loop and current loop for simulation. Then simulating iterative learninglaw and comparing the performance of two algorithms synchronization control.