The Design And Verification Of10G EPON MAC Layer On ONU Side

10G EPON meets the growing demand for high-bandwidth with better economyand also can learn from the mature technologies of EPON in the operation,maintenanceand scale of deployment.So that10G EPON becomes the next generation opticalaccess technologies favored by global operators.Since the MAC lay protocol is thecore and difficulty of10G EPON standard,MAC layer implementation has alsobecome the key technologies to achieve the10G EPON system.The paper devotes tothe design implementation and verification of10G EPON MAC layer on the ONUside,according to the technology roadmap that consist of four steps asfollowing:research on the protocol,feature point extraction,logic implementation,functional verification.The program supports both symmetric mode and asymmetricmode working condition.Firstly,detailed analysis of10G EPON standard is present in the thesis.After10GEPON protocol is introduced and the modified and developed part is explained incontrast with EPON,the thesis makes a research on the key technologies includingsystem synchronization,ranging and delay compensation,logical topology simulation.Then as the core content of the MAC layer protocol,multi-point control protocol iselaborated which includes the discovery process,the gating process,the reportingprocess.Finally,according to the particular application situation of ONU MAClayer,the concrete design requirements is analyzed.Followed, after the completion of the design requirements analysis, the design andimplementation of MAC layer on the ONU side are completed. Based on the top-downdesign ideas to complete the division of the functional modules of the MAC layer,which consists of the following three second class modules:downstream framereception processing module,gating control signals generation module,upstream framescheduling and transmitting module. Then the detailed design and implementation ofthe sub-modules is illustrated.While the design of the difficulty are analyzed, includingthe FCS check design principle, the downstream data path buffer module design principle,the gating control signals generating design principle,the data frametransmission buffer design principle and upsteam scheduling design principles.Finally, to complete the verification of the logical design using System Veriloglanguage to create a verification environment based on the VMM.Verification platformdesigned in this paper has a high automatic checking characteristics, which is not onlyto achieve the automatic checking of the upstream and downstream packet, but alsoable to realize automatic checking of granting control signal generated by generatingmodule and timing signal generated by scheduling module.This technique greatlyimproved the efficiency of the verification.The chip developed by this ASIC project that the subject comes from hassuccessfully taped out.And the result of the hand-shake test with OLT show that ONUdesigned in this thesis can be successful on-line and registered in the symmetric modeand asymmetric mode. The effectiveness of the work done is demonstrated.