Research And Implementation On FPGA Based Real-time Specific Speech Recognition System

Specific speech recognition，means to recognize the same or similar speech segments whichare given in the template library at the dynamic voice stream. As a branch of the specific audioretrieval, specific speech recognition can used to detect garbage voice in the telecommunicationsnetwork and other fields, such as advertisement detection and copyright protection. With theincreasing number of templates, the specific speech recognition system is faced with thechallenge of real-time performance. While the real-time performance means multi-channelreal-time processing capabilities of the system, which is the key point for the system to be putinto practicality.This dissertation relies on the key project in information and technology domain of theNational863Program, combining with the real-time and multi-access needs over thetelecommunications network. Aiming at reaching the real-time performance under the conditionof high-capacity voice template library (template numbers more than8000), the main work andachievements of this dissertation can be outlined as follows:1．A multi-processing element parallel architecture based on the superscalar architecture isproposed. This architecture fully excavates the parallelism of the specific speech recognitionalgorithm. It employs the super-word parallel technology in the processing element. We designeda data processing unit of256bits, in the condition of the units of frame in the voice signalprocessing and the max parallelism degree8of the super-word parallel. The parallelmulti-processing units use the superscalar architecture. As every processing element canaccomplish the matching processing, the architecture is scalable.2．Putting forward data storage and scheduling mechanism to make the each processingelement in the architecture to do their best anytime. For the template data storage, we study ahybrid storage structure of the combination of centralized shared storage and distributed storage,and we design the secondary storage mechanism of the template data and PE internal doublebuffer (Double buffer DB) structure, to achieve the efficient data storage system. We study thetemplate distribution strategy of a round robin distribution mechanism and a first request firstdistribution mechanism for the template data distribution.3．In order to solve the problem of excessive IP (Intellectual Property) usage whencalculating large-size squares using embedded multipliers in FPGAs directly, this thesis presentsan efficient method for square calculation. The proposed method first through a simple iterativelogic circuit to reduce the width of operands, then combined with the embedded DSP48E tocomplete square calculation. Experimental and simulation results show that the method can getgood results in reducing the usage of DSP48E. 4．Combining with MicroBlaze processor embedded in Xilinx’s FPGA, making the proposedprocessing architecture as a co-processor, we realize the specific speech recognition SOPCsystem on an FPGA platform. The system uses the shared RAM interface mode based on theAXI4Bus protocol to realize the control and data exchange between the main processor and thecoprocessor. By testing the performance of the system and doing the resources analysis, we getthe results that the system fulfill the22-access real-time recognition tasks instantaneously withthe number of templates is8192, realize the multi-access real-time processing under thecondition of large-capacity template library.