Research On The Algorithm Of Digital Multi-Beamforming And Its FPGA Implementation

Navigation receiver plays an important role in military field and our daily life.However, it usually receives interference signals in lower power environment, whichcould lead to failure. According to this problem, this thesis researches someanti-interference measurements based on spatial filtering. It is elaborated that the studyof beamforming algorithm, the robust beamforming algorithm and the efficientimplementation of hardware. The test results illustrate that this system could suppressinterference signals effectively. The main content of this thesis, including four areas, asfollows.1. According to the hardware platform and requirements of the project, twobeamforming algorithms including MVDR algorithm and LCMV algorithm areanalyzed. Algorithms are simulated in real environment. Three robust beamformingalgorithms including diagonal loading, steering vector uncertainty set and wide nullingare analyzed and simulated for improving the robustness of algorithm. Calibration ofchannels and compensation of array mutual coupling which are fitting for hardwarerealization are analyzed to ensure the performance of system would not fall sharply intiny mismatch situation.2. The hardware system architecture of digital multi-beamforming algorithm areintroduced on the basis of theoretical analysis and computer simulation. Under thepremise of meeting the requirements of system, simple and efficient way is adopted tothe implementation of all modules. Analytical signal is constructed by digital mixingand low-pass filter. The solving of optimum weight vector and beamforming ofalgorithms are implemented. Floating-point calculations are employed in parts of thecalculation process to improve accuracy of algorithm. Calibration of channels andcompensation of array mutual coupling are realized by look-up table. All codes areimplemented by Verilog language.3. The improvement measures of the FPGA complementation ofmulti-beamforming are researched. An equivalent method of matrix inversion which replacing inverse matrix with adjoint matrix is introduced and serial structure whichmultiplexed multiplier is used for solving weight vector to reduce the computationalcomplexities of multi-matrix inversion and weight update, and also the consumption ofhardware resources. The utilization ratio of FPGA is raised by improving the systemclock frequency.4. All modules of digital beamforming algorithm pass through the joint tests. Thetest results illustrate that the algorithms are suitable for the system and able to realize onhardware platform.