The FPGA Design And Implementation Of CLEAN Technology In Random Sparse Array

In the field of radar imaging, the use of large receiver arrays can get very highangular resolution. However, large receiver arrays have problem of high cost of itselfand a large amount of data, and maybe it can produce fuzzy grating lobe. Takingconsideration of lowing cost, reducing data processing and avoiding grating lobes, it isessential to thin and randomlize the antenna array, which would incese the peaksidelobe and mean sidelobe. Using CLEAN technology can effectively eliminate theinfluence of high sidelobe of random array and improve image contrast and dynamicrange, improved image quality. With the continuous development of FPGA technology,high-density, high-performance FPGA provides a good platform for implementation ofthe CLEAN algorithm. The implemebtation of CLEAN algorithm with FPGA is of greatsignificance for real-time processing of radar imaging of the random array.This dissertation focused on studying the CLEAN technology of random thinningarray signal processing and its design and implementation in FPGA device. The maincontents were as follows:1.Introduce Random matrix theory, analyse the reason of hign sidelobe、falsetargets and objectives divison in random array. Make the description of CLEANalgorithm in the random sparse array, show a flow diagram of the algorithm,finish theresearch on Image domain and E domain. Make the comparison of the two algorithms,get the conclusions that the image domain processing is more suitable forimplementation in FPGA device.2.Finish the design and implementation of some important basic modules of theCLEAN algorithm including CORDIC modulo, the sine and cosine module, and basicsingle-precision floating-point arithmetic module and floating point square root module.The CORDIC module completed design of vector mode, rotating mode, thefloating-point add(sub) use Dual-channel design mode. The floating-point square rootusing the design of a Taylor series approximation and improve the operation accuracy.Complete the basic module timing simulation and do error analysis. The error analysis results shows that the module on the above have a high degree of accuracy.3.Finish system-level design and implementation in FPGA device of CLEANalgorithm. Detail the structures of the various modules of the system such as iterativecontrol and calculation module, peak detector, DBF module, the main lobe imagingmodule, show simulation results of each module. Finish the system’s timing simulation,analyze the simulation results and Compare the result which importing data fromsimulation into Matlab and the result of Matlab and finish the error analysis.