Key Technology Research On Double-Layer Networked Instrument Bus

For the miniaturization of Multi-CPU system, this paper proposes a Networked Instrumental Bus with Double-Layer Arbitration(NIBDA) in both hardware and protocol layer.The main innovations of this paper are as follows:Firstly, with arbitration in hardware layer, the NIBDA features a multi-host network topology by sharing a single set of transmitter/receiver among internal and external nodes. Secondly, the NIBDA has achieved automatic switching between central clock mode and source synchronous clock mode in a single clock signal line which simplifies the bus architecture. Finally, this paper proposes a dynamic priority scheduling method, which effectively solved the transmission delay problem of the low-priority nodes in the bus network with a large number of control nodes, and improved the real-time performance of the NIBDA.This paper is divided into six chapters:Chapter1introduced the development situation of instrumental bus, followed by a briefing of this project.Chapter2devised a NIBDA system design, including system concept, hardware structure and protocol framework.Chapter3is the primary chapter. It discussed the key technics of NIBDA system, and devised the implementation of arbitration in hardware layer, clock sharing, and dynamic priority distribution. In addition, error control of the NIBDA system is discussed in the later part of this chapter.Chapter4discussed the implementation of the double-layer arbitration, including the hardware design of transmitter/receiver sharing, and the FPGA module in bus management.Chapter5presented a NIBDA system test, including arbitration in both hardware layer and protocol layer, clock mode switching in a single clock source. In addition, a simulation test is designed to assess the performance of the dynamic priority distribution.Chapter6concluded this paper, and gave expects for further research.