Technology Analysis Of Wafer Chemical Mechanical Polishing Tungsten Stuff In The Manufacture Of ULSI

CMP is Enabling Technology for Advanced Semiconductor Devices.Leading edgeintegrated circuits (ICs) are complicated structures designed to have up to3cappinglayers above a low k dielectric material. The upper capping later may use TEOS and/orsilicon nitride (SiN) while the lower one may use silicon carbon nitride (SiCN), siliconcarbide (SiC), or carbon dopped oxide (CDO) immediately above the low kdielectric.Therefore, a barrier slurry for copper CMP, in addition to exhibition a high removal rateof the barrier, must be able to remove the upper capping layer and stop at the underlyingdielectric surface.Rohm and Haas Electronic Materials has developed a slurry family that caneffectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of thesefilms, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC,depending on the specific slurry design. Removal rates at low down force, and are ateither high or low pH, in order to satisfy a variety of industry requirements. Most of theslurries are tunable with one or two additives to control the removal rates of the films.It is noted that there is a thin fluid film between the loaded asperities and the waferbeing polished in CMP process, there by a flow system with nano scale film is formedin. To explore the feat ures in such cases will lay the foundation of mechanism ofCMP. One key challenge p rovided by CMP is the analysis on temperat ure field withsuper thin film...