Hardware Design And Implementation Of Image Match Algorithm Based On Genetic Algorithm

Image matching technology widely used in many fields is becoming more andmore important in the field of image information process and has a high research andapplication value. With the rapid development of microelectronics and integrated circuittechnology, the field programmable gate array (FPGA) integration and performance hasbeen significantly improved. The image matching algorithm implemented in hardwarecan significantly improve matching speed through the use of FPGA powerful parallelprocessing capabilities. Therefore, the hardware implementation of image matching as anew research focus has been widespread concern.The topic stems from the laboratory subject “CT Image Match TechnologyResearch”. This thesis, in-depth research and software verification of a variety of imagematching algorithms, proposes normalized product correlation as the similarity functionwith genetic algorithm-based search strategy image matching algorithm, and thenpresents the hardware structure of image matching based on the genetic algorithm. Thisthesis mainly consists of the following three parts:Firstly, compare the accurate matching rate, speed, and noise immunity of a varietyof matching algorithms such as SSDA, FFT phase correlation and pyramidmulti-resolution through the software simulation. On this basis, focus on the principlesand characteristics of the genetic algorithm and propose image matching algorithm, thenverify that the improved matching algorithm is faster than the traditional matchingalgorithm without the loss of the matching rate.Secondly, focus on the analysis of each structure, resources and speed of the fullybuffer, single window partial buffer and multi-window partial buffer, and then propose aconfiguration coefficient image filtering hardware design based on the multi-windowbuffer. Complete RTL code using Verilog HDL and prove the correctness of its functionthrough functional simulation in Modelsim, then be verified in Xilinx Virtex-Ⅱ ProFPGA development platform.Finally, design the parallel hardware structure of image match based on the geneticalgorithm and mainly analyze the principle and implementation of the pseudo-randomnumber generator. Discuss the matching result of different bit widths fixed points andpropose the hardware structure of normalized cross correlation. The matching systemverification is completed in Xilinx Virtex-Ⅱ Pro FPGA platform and the result showsthat the maximum clock frequency of the design is up to110.679MHz.This thesis has achieved the image matching high-speed design based on geneticalgorithm, meeting the requirements of real-time processing. Matching speed is up to 30.72ms at66.7MHz clock with the size of source image256256and the size oftemplate image3232and with the literature [17-18], the performance hassignificantly improved.