The Design Of Clock Partial Test Board Of High Frequency And High Precision

As cloud computing services arises at the historic moment, the application of cloudcomputing is more popular, in order to deal with huge data information exchange, traditionalEthernet switches have been gradually can not meet the requirements of the technology andservice. The next generation of core data exchange products should provide the ability of hugeinformation processing and continuous bandwidth upgrading. And with the increase of datacommunications business, the data traffic of every single veneer is increased, the complexity ofthe design of veneer will also be increased accordingly, and the number of veneer’s layer will beincreased, from a dozen increased to more than twenty, the number of veneer’s PIN will beincreased and the linear density of the device is becoming more and more high, in addition, asthe processing speed of veneer data information increasing, the frequency of the clock signals arebecoming more and more high, these can make the clock signal interference phenomenonseriously. This will pose challenges for veneer normal work.In order to make sure that each index of veneer can work normally, the various professionaltesting is needed to verify, one of them is the clock stress test which is very important, it is theessential link which to verify the veneer of fault tolerance and tolerance ability. The clock phasejitter, frequency precision and phase partial tolerance are the key indicators to measure thestability of the products. So we design the clock partial test veneer which meets these testrequirements. This test veneer can realize output these level clock signals: LVDS、HSTL、LVTTL、LVCMOS.The clock signal is “clean”, that means the signal can not have big shaking,burr, overshoot, steps and other bad phenomena. And at the same time, it has the function of thesignal delay and phase shift trigger. We design the maximum output clock frequency600MHz, itcan basic satisfy the most testing requirements of the clock signals of the veneers.The clock converter IC which is on the clock partial test veneer is AD9558, which comesfrom ADI (Analog Device Inc., The analog device companies in the United States.) company. Itcan provide four road input ports and six road output ports, can meet the design requirements inthe vast majority of application scenarios basically. The chip can realize outputting fullyprogrammable clock signals, and can make the jitter attenuation. The device is suitable for awide range of cable communication applications, including synchronous Ethernet (SyncE) andsynchronous optical network (SONET/SDH), the chip can convert any standard input frequencyto any standard output frequency from352Hz to1.25GHz. This new clock converter is superiorto the traditional PLL(Phase Locked Loop), because it don’t need additional expensive VCXO(Voltage Control X-tal Crystal Oscillator). In addition, AD9558supports asynchronous mapping and asynchronous solution mapping, and other adaptive clock application, it can make the outputfrequency which in nominal output frequency±100ppm dynamic adjustment, without the needfor manual interruption internal DPLL (Digital Phase Locked Loop).According to the results of the final test veneer performance debugging, we can sure theclock partial test veneer can ouput the following level: LVDS、HSTL、LVTTL、LVCMOS, canreceive the following level:LVTTL、LVPECL、CML、LVDS, can achieve the function of1~65535ms trigger delay, and can satisfy the realization of0~360degrees (0ps~5×108ps) phaseshift, can output maximum600MHz clock, can achieve frequency changes with the minimumstep1Hz. Clock partial test board is an innovative design, with the clock partial test veneer,engineers can test the reliability and stability of the veneer efficiently and easily. It also can winthe precious time for the development of the veneer, accelerate the speed of development, it hasimportant theoretical and practical value.