Design And Implementation Of OFDM Timing Synchronization Based On Ieee802.11A On FPGA

Orthogonal Frequency Division Multiplexing (OFDM) was presented in the1950s, and has been adopted by more and more international standards during nearly60years of development. Due to its high spectrum efficiency which can be effective against multipath effects and frequency selective fading, and many other prominent advantages, OFDM is widely applied in broadband wireless access systems, became one of the key technologies of the fourth-generation mobile communication and has become an important topic in the field of mobile communications. The performance of OFDM synchronization impacts on the overall performance of the OFDM communication system directly, so OFDM synchronization is the premise of OFDM communication system.This topic of the thesis came from the National863project, which included the design and implementation of OFDM synchronization based on IEEE802.11a standard. OFDM synchronization contains timing synchronization, carrier synchronization and sampling clock synchronization. Because the timing synchronization is the first step of the entire OFDM synchronization operation, this thesis mainly researched on its modeling, simulation and hardware implementation.Firstly, this thesis briefly introduced the research background, significance, domestic and foreign development status and prospects. It briefly expounded the basic principle as well as the advantages and disadvantages of OFDM, and discussed the impact of the timing synchronization deviation of OFDM system in detail. Secondly, designed a Simulink model of an OFDM baseband transmitter to generate the OFDM baseband signal, including the short training sequence, the long training sequence and the valid data symbols. Thirdly, determined the OFDM timing synchronization scheme through the simulation and analysis of several common OFDM timing synchronization algorithm. Besides designed its Simulink model and System Generator model, which made it be more easy to be implemented on FPGA. In order to capture the OFDM baseband signal and transmit them to the FPGA, designed a high-speed data acquisition card with good performance. Finally, used Verilog HDL to describe the algorithm of OFDM timing synchronization to map it to the logic circuits, according to its System Generator model.This thesis focused on the modeling of the OFDM timing synchronization algorithm, and made much improvement of the logic circuits mapped from it. Therefore, this design focused on how to make better implementation of OFDM timing synchronization on FPGA. Making improvments of some important module reduced the difficulty of its hardware realization, and also greatly enhanced the performance of the OFDM timing synchronization while reducing the consumption of the FPGA logic resources. At last, through actual test, it proved that OFDM timing synchronization was implemented on FPGA.