Turbo Iterative Synchronization Technology With Multi-core Dsp Implementation And Optimization

As an excellent means of channel coding, Turbo codes have been approaching the channel capacity with high reliability and effectiveness in a variety of low SNR situations. This article, for example, using the tail biting convolution code encoder after interleaving make out the greatest degree of randomness coding, which is consistent with the conditions of approaching the Shannon limit. In some cases, however, like extremely bad channel conditions, along with the Doppler frequency shift as well as other types of frequency offset and nonlinear distortion, system is likely to result in poor performance of the receiver. Once synchronization or tracking failed, it will cause a wide range of error propagation, resulting in unpredictable consequences. Therefore the establishment of a low signal to noise ratio of the synchronization mechanism is particularly important.Turbo decoder has natural bodies of iterations. Each iteration results of the decoding can be regarded as the input of the next iterative decoding. Reliability of information after each decoding has been improved. Iterative synchronization technology is based on this architecture. The use of the Turbo iterative soft decoder output as a priori information help figure out timing error estimates. After the adjusted samples value sequence is pushed out from synchronizer, they are re-poured into the Turbo decoder. So on ad infinitum, the soft information used by the Turbo decoder synchronizer become more reliable and thus more reliable a priori information is used by the synchronizer, which forms a positive feedback.In addition, the article focuses on the simultaneous iterative algorithm on the latest release of TTs C66x series of multi-core DSP implementation and optimization. C66x has a computing speed, less resource-intensive, rich external interfaces. Each second there can be done816×16or432×32fixed-point multiplication and other adder or logic operation, clocking at up to1.25GHZ x8. The eight-core architecture allows the computation and the degree of parallelism have large-scale upgrade. In addition, the C66x have larger RAM space:eight cores, each with512K of local L2RAM, all nuclear at the same time share a size4M shared memory space. The plug-in DDR3512MB of memory size, can support large amounts of data cache and backup usage.To improve the efficiency of code to achieve high performance, the c6678code optimization and cache allocation in the last two chapters focusing on the Turbo iterative algorithm is discussed. The use of inline instructions, data block placement and data aligning all have a significant influence on execution.