High-Frequency Power Integrity Analysis

In the past decade, with the development of lithography, as well as the improvement of packaging technology, integrated circuit also into the nano-stage.devices size are getting smaller and integration are getting more intensive, now we could integrate millions of logic gates on silicon of100nm at present technology level; with the clock frequency increasing, the electromagnetic wavelength could be compared with the size of devices, signal reflection/crosstalk and simultaneous switching noise of the power supply network is getting stronger, becoming the major problem to the signal integrity; with the reduction of the amplitude of the voltage and the increasing of the current, the stability requirement to power network is getting more strict. So whether or not to provide a clean power to transistors will become critical. The paper firstly from the power supply network voltage regulator modules, printed circuit boards, packaging and planar structure talks about power integrity discussion. Using the resonant analysis and impedance analysis to detect the rationality of the power network, by adding decoupling capacitors to optimize the power network, reduce the voltage overshoot, ground bounce and oscillation phenomenon. Then talks about Chip power grid structure network, according to the symmetry of the power grid continuum, continuum equations calculated by the finite difference node, on the the ideal borders and the free boundary grid continuous system simulation, testing power fluctuations and spice simulation comparison, in the same circumstances, the continuous system simulation results more accurate and intensive computational grid.